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HI3086
August 1997
6-Bit, 140 MSPS, Flash A/D Converter
Description
The HI3086 is a 6-bit, high-speed, flash analog-to-digital converter optimized for high speed, low power, and ease of use. With a 140 MSPS encode rate capability and full-power analog bandwidth of 200MHz, this component is ideal for applications requiring the highest possible dynamic performance. To minimize system cost and power dissipation, only a +5V power supply is required. The HI3086's clock input interfaces directly to TTL, ECL, or PECL logic and will operate with singleended inputs. The user may select 16-bit demultiplexed output or 8-bit single-channel digital outputs. The demultiplexed mode interleaves the data through two 8-bit channels at 1/2 the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces, while allowing the A/D converter to be clocked to the full 140 MSPS conversion rate. Fabricated with an advanced bipolar process, the HI3086 is provided in a space-saving 48-lead MQFP surface mount plastic package and is specified over the -20oC to 75oC temperature range.
Features
* Differential Linearity Error. . . . . . . . . . . . . . . . . 0.2 LSB * Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.2 LSB * Single +5V Power Supply Operation Available * Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 7pF * Wide Analog Input Bandwidth . . . . . . . . . . . . . 200MHz * Low Power Consumption . . . . . . . . . . . . . . . . . .360mW * CLK/2 Clock Output Pin * Excellent Temperature Characteristics * 1:2 Demultiplexed Output * Internal 1/2 Frequency Divider Circuit (With Reset Function) * Compatible with ECL, PECL and TTL Digital Input Levels * Direct Replacement for Sony CXA3086
Applications
* RGB Graphics Processing (LCD, PDP) * Digital Communications (QPSK, QAM) * Magnetic Recording (PRML)
Ordering Information
PART NUMBER HI3086JCQ HI3086EVAL TEMP. RANGE (oC) -20 to 75 25 PACKAGE 48 Ld MQFP PKG. NO. Q48.12x12-S
Evaluation Board
Pinout
HI3086 (MQFP) TOP VIEW
CLKOUT INV SELECT DGND1 DVCC2 DVCC1 DGND1 DVCC1 DVCC2
DGND2 P2D0 (LSB) P2D1 P2D2 P2D3 P2D4 P2D5 (MSB) DGND2 DVCC2 RESETN/T RESET/E RESETN/E
1 2 3 4 5 6 7 8 9 10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
NC PS
NC
DGND2 P1D5 (MSB) P1D4 P1D3 P1D2 P1D1 P1D0 (LSB) DGND2 DVCC2 CLK/T CLKN/E CLK/E
11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VIN AVCC
VRBS VRB
AGND
AVCC
VRT VRTS
NC
AGND
DGND3
DVEE3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
4110.1
4-1406
HI3086 Functional Block Diagram
AVCC 17 20 VRTS VRT 22 R1 21 R 1 R LATCH A TTLOUT 2 34 P1D4 33 P1D3 32 P1D2 31 P1D1 30 6-BIT LATCH 30 P1D0 (LSB) ENCODER 31 R 32 R (MSB) 33 7 6 LATCH B R 62 R 63 R2 VRB VRBS 16 15 DELAY R 2 P2D0 (LSB) TTLOUT 6-BIT 5 4 3 P2D5 P2D4 P2D3 P2D2 P2D1 6-BIT 6-BIT (MSB) 35 P1D5 INV 42 DVCC1 38 47 DVCC2 9 28 37 48 DGND3 24
6-BIT R R VIN 19
CLK/T CLK/E CLKN/E
27 25 26
18 40 NC 45
D RESETN/T RESETN/E RESET/E 10 12 11 14 23 AGND 44
Q SELECT Q 43 CLKOUT
41 SELECT
39
46
1
8
29 36
13 DVEE3
PS
DGND1
DGND2
4-1407
HI3086 Pin Descriptions
PIN NO. 14, 23 TYPICAL VOLTAGE LEVEL GND
SYMBOL AGND
I/O
EQUIVALENT CIRCUIT
DESCRIPTION Analog Ground. Separated from the digital ground. Analog Power Supply. Separated from the digital power supply. Digital Ground.
17, 20
AVCC
+5V (Typ)
1, 8, 29, 36, 39, 46 9, 28, 37, 38, 47, 48 24
DGND1 DGND2
GND
DVCC1 DVCC2
+5V (Typ)
Digital Power Supply.
DGND3
+5V (Typ) (With a Single Power Supply) GND (With Dual Power Supplies)
Digital Power Supply. Ground for ECL input. +5V for PECL and TTL input.
13 DVEE3
GND (With a Single Power Supply) -5V (Typ) (With Dual Power Supplies)
Digital Power Supply. Ground for ECL input. -5V for PECL and TTL input.
18, 40, 45 25 26
NC
No Connect pin. Not connected with the internal circuits. I I ECL/PECL
DGND3
CLK/E
Clock input. CLK/E Complementary Input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. Reset Input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset.
1.2V R DVEE3 R
CLKN/E
12 25 11 26
R
R
12 RESETN/E
I
11 RESET/E
I
RESETN/E Complementary Input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation.
4-1408
HI3086 Pin Descriptions
PIN NO. 27 10 (Continued) TYPICAL VOLTAGE LEVEL TTL
SYMBOL CLK/T RESETN/T
I/O I I
EQUIVALENT CIRCUIT
DVCC1 R/2
DESCRIPTION Clock Input. Reset Input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset.
10 27 1.5V R DGND1 DVEE3
42
INV
I
TTL
DVCC1
Data Output Polarity Inversion Input. When left open, this input goes to high level. (See Table 1; I/O Correspondence Table). Power Saving Input. When the input is set to low level, the power saving mode is set. In this time the all TTL ouputs go into the high impedance state. Normally, set to high level or left open.
44
PS
I
TTL
42 44
DGND1 DVEE3
41
SELECT
VCC or GND
DVCC1
Data Output Mode Selection. (See Table 2, Operating Mode Table).
41
DGND1 DVEE3
4-1409
HI3086 Pin Descriptions
PIN NO. 22 (Continued) TYPICAL VOLTAGE LEVEL +4.0V (Typ)
22 R1
SYMBOL VRTS
I/O O
EQUIVALENT CIRCUIT
DESCRIPTION Reference Voltage Sense. Bypass to AGND with a 0.1F chip capacitor. Top Reference Voltage. Bypass to AGND with a 1F tantal capacitor and 0.1F chip capacitor.
21
VRT
I
VRTS + R1 x IREF
21 R COMPARATOR 1
16
VRB
I
VRBS -R2 x IREF
R R
Bottom Reference Voltage. Bypass to AGND with a 1F tantal capacitor and a 0.1F chip capacitor.
COMPARATOR 2
15
VRBS
O
+2.0V (Typ)
R
Reference Voltage Sense. Bypass to AGND with a 0.1F chip capacitor.
R COMPARATOR 62 R R COMPARATOR 63 R R2 16 15
19
VIN
I
VRT to VRB
AVCC
COMPARATOR AVCC
Analog Input.
19
VREF
AGND DVEE3
30 to 35 2 to 7 43
P1D0 to P1D5 P2D0 to P2D5 CLKOUT
O O O
TTL
DVCC1 DVCC2
Port 1 Side Data Output. Port 2 Side Data Output. Clock Output. (See Table Operating Mode Table.) 2.
2 TO 7 30 TO 35 100K 43 DGND2 DVEE3
DGND1
4-1410
HI3086
Absolute Maximum Ratings
(TA = 25oC)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only)
Supply Voltage . . . . . . . . . . . (AVCC , DVCC1 , DVCC2) -0.5V to 7.0V (DGND3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V (DVEE3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to 0.5V (DGND3 - DVEE3) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . VRT - 2.7V to AVCC Reference Input Voltage (VRT) . . . . . . . . . . . . . . . . . . .2.7V to AVCC (VRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 2.7V to AVCC (|VRT - VRB|) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage ECL (***/E (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . DVEE3 to 0.5V PECL (***/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DGND3 TTL (***/T, INV PS) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1 Other (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1 VID (|***/E - ***N/E| (Note 3)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V
Recommended Operating Conditions
WITH A SINGLE POWER SUPPLY MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . -0.05 0 +0.05V DGND3 . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DVEE3 . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V Analog Input Voltage (VIN) . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . 1.4 +2.6V |VRT - VRB |. . . . . . . . . . . . . . . . . . 1.5 2.1V Digital Input Voltage ECL (***/E) VIH . . . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V PECL (***/E) VIL DGND3 . . . . . . . DGND3 - 3.2 DGND3 - 1.4V TTL (***/T, INV, PS) VIH . . . . . . . . 2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . 0.8V Other (SELECT) VIH . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . DGND1 VID (Note 3) (|***/E- ***N/E|) . . . . . 0.4 0.8 Max Conversion Rate (fC , Straight Mode) . . . 100 Units = MSPS Max Conversion Rate (fC , DMUX Mode) . . . . 140 Units = MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC WITH DUAL POWER SUPPLIES MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . -0.05 0 +0.05V DGND3 . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V DVEE3 . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V Analog Input Voltage (VIN) . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . 1.4 +2.6V |VRT - VRB| . . . . . . . . . . . . . . . . . . 1.5 2.1V Digital Input Voltage ECL (***/E) VIH DGND3 . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V ECL (***/E) VIL DGND3 . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . 0.8V Other (SELECT) VIH . . . . . . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . . . . . . DGND1 VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . 0.4 0.8 Max Conversion Rate (fC , Straight Mode) . . . 100 Units = MSPS Max Conversion Rate (fC , DMUX Mode) . . . . 140 Units = MSPS Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. ***/E and ***T indicate CLK/E and CLK/T, etc. for the pin name. 3. VID: Input Voltage Differential.
Electrical Specifications
PARAMETER Resolution DC CHARACTERISTICS Integral Linearity Error Differential Linearity Error
DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC, PECL Input SYMBOL TEST CONDITIONS MIN TYP 6 MAX UNITS Bits
EIL EDL
VIN = 2VP-P , fC = 5 MSPS
-
-
0.2 0.2
LSB LSB
4-1411
HI3086
Electrical Specifications
PARAMETER ANALOG INPUT Analog Input Capacitance Analog Input Resistance Analog Input Current REFERENCE INPUT Reference Resistance (Note 5) Reference Current (Note 6) Residual Resistance RREF IREF R1 R2 DIGITAL INPUT (ECL, PECL) Digital Input Voltage: High Digital Input Voltage: Low Threshold Voltage Digital Input Current: High Digital Input Current: Low Digital Input Capacitance DIGITAL INPUT (TTL) Digital Input Voltage: High Digital Input Voltage: Low Threshold Voltage Digital Input Current: High Digital Input Current: Low Digital Input Capacitance DIGITAL OUTPUT (TTL) Digital Output Voltage: High Digital Output Voltage: Low Leakage Current SWITCHING CHARACTERISTICS Maximum Conversion Rate Aperture Jitter Sampling Delay Clock High Pulse Width Clock Low Pulse Width Reset Signal Setup RESET Signal Hold CLKOUT Output Delay Data Output Delay (Note 7) fC tAJ tDS tPW1 tPW0 tRS tRH tDCLK tDO1 tDO2 Output Rise Time Output Fall Time tr tf 0.8V to 2.0V 0.8V to 2.0V DMUX Mode CLK CLK RESETN - CLK RESETN - CLK (CL = 5pF) (CL = 5pF) (CL = 5pF) (CL = 5pF) (CL = 5pF) DMUX Mode 140 3 2.9 2.9 3.5 0 3.5 t (Note 6) 4.5 10 4.5 7 t+1 8 2 2 6 9 t+2 10 MSPS ps ns ns ns ns ns ns ns ns ns ns VOH VOL IOZ IOH = -2mA IOL = 1mA Power Saving Mode 2.4 -15 0.5 70 V V A VIH VIL VTH IIH IIL VIH = 3.5V VIL = 0.2V 2.0 -50 -500 1.5 0.8 0 0 5 V V V A A pF VIH VIL VTH IIH IIL VIH = DGND3 -0.8V VIL = DGND3 -1.6V DGND3 -1.05 DGND3 -3.2 -50 -75 DGND3 -1.2 DGND3 -0.5 DGND3-1.4 +50 0 5 V V V A A pF 160 6.5 3.0 3.0 225 9.0 4.2 4.2 308 12.5 5.7 5.7 mA CIN RIN IIN VIN = +3.0V + 0.07VRMS 16 0 7 150 125 pF k A DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC, PECL Input (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
4-1412
HI3086
Electrical Specifications
PARAMETER DYNAMIC CHARACTERISTICS Input Bandwidth S/N Ratio VIN = 2VP-P , -3dB fC = 140 MSPS, fIN = 1kHz Full Scale, DMUX Mode fC = 140 MSPS, fIN = 34.999MHz Full Scale, DMUX Mode Error Rate fC = 140 MSPS, fIN = 1kHz Full Scale, DMUX Mode Error > 4 LSB fC = 140 MSPS, fIN = 34.999MHz Full Scale, DMUX Mode Error > 4 LSB fC = 100 MSPS, fIN = 24.999MHz Full Scale, Straight Mode Error > 4 LSB POWER SUPPLY Supply Current Supply Current Power Consumption (Note 9) Supply Current Power Consumption NOTES: 4. RREF: Resistance value between VRT and VRB . V RT -V RB 5. I REF = --------------------------- . R REF 1 6. t = ---- . fC 7. TPS: Times Per Sample. ( V RT -V RB ) 2 8. P D = ( I CC + I EE ) * V CC + ----------------------------------- . V
REF
DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC, PECL Input (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
200 -
37.0
-
MHz dB
-
34.5
-
dB
-
-
10-12
TPS (Note 8)
-
-
10-9
TPS
-
-
10-9
TSP
ICC IEE PD ICC + IEE PD Power Saving Mode Power Saving Mode
54.0 0.4 290 2.0 28.0
67.5 0.6 360 -
90.0 0.8 470 8.0 58.0
mA mA mW mA mW
4-1413
HI3086
DGND3
VIH (MAX)
VIL VTH (DGND3 - 1.2V) VID VIH
VIL (MIN)
FIGURE 1. ECL AND PECL SWITCHING LEVEL TABLE 1. I/O CORRESPONDENCE INV 1 VIN VRTS STEP 63 62 * * * 32 31 * * * 1 VRBS 0 D5 D0 D5 0 D0
63 62 61 60 59 58 STEP 1 LSB
111111000000 111110000001 * * * * * *
100000011111 011111100000 * * * * * *
5 4 3 2 1 0
R1 x IREF
R2 x IREF
000001111110 000000111111
VRT VRTS
VIN
VRBS VRB
FIGURE 2.
Test Circuits
100MHz 5V A ICC 4V VRT AVCC DVCC1 DVCC2 5V A IEE AMP OSC1 : VARIABLE
DGND3
fR 1.95V VIN CLK/E 5MHz PECL
VIN HI3086 CLK
6
LOGIC ALALYZER 1024 SAMPLES
2V
VRB
DGND2 DGND1 AGND
OSC2 DVEE3 ECL BUFFER 100MHz
FIGURE 3. CURRENT CONSUMPTION MEASUREMENT CIRCUIT
FIGURE 4. SAMPLING DELAY MEASUREMENT CIRCUIT APERTURE JITTER MEASUREMENT CIRCUIT
4-1414
HI3086 Test Circuits
(Continued)
+V S2 VIN VRB + VRT
-
S1
S1: ON WHEN A < B S2: ON WHEN A > B
CLK 33 32 31 30 (LSB)
-V AB COMPARATOR VIN HI3086 6 A6 TO A1 A0 B6 TO B1 B0 6 BUFFER CLK "1" 00...00 TO 11..10 VIN
t
29 SAMPLING TIMING FLUCTUATION (= APERTURE JITTER)
"0" DVM
CONTROLLER
NOTE: Where (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter Tai is: 64 t AJ = / ------- = / ----- x2f . 2 T FIGURE 6. APERTURE JITTER MEASUREMENT METHOD
FIGURE 5. INTEGRAL LINEARITY ERROR MEASUREMENT CIRCUIT DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT
SIGNAL SOURCE fC 4
VIN HI3086
6 LATCH
A
COMPARATOR A>B
PULSE COUNTER
-1kHz
CLK
CLK + LATCH
B
2VP-P SINE WAVE 4 LSB SIGNAL SOURCE fC
1/ 8
FIGURE 7. ERROR RATE MEASUREMENT CIRCUIT
Operating Modes
The HI3086 has two types of operating modes which are selected with Pin 41 (SELECT).
TABLE 2. OPERATING MODE OPERATING MODE DMUX Mode Straight Mode SELECT VCC GND MAXIMUM CONVERSION RATE 140 Mbps 100 Mbps DATA OUTPUT Demultiplexed Output 70 Mbps Straight Output 100 Mbps CLOCK OUTPUT The input clock is 1/2 frequency divided and output at 70MHz. The input clock is inverted and output at 100MHz.
Demux Mode (See Figures 19, 20, 21). Set the SELECT pin to VCC for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin.
When using multiple HI3086 units in parallel in this mode, differences in the start timing of the 1/2 frequency divided clock may cause operation as shown in Figures 8 and 9. As a countermeasure, the HI3086 is equipped with a function which resets the 1/2 frequency divided clock. When resetting this clock, the RESET pulse must be input to the RESET pin. See the Timing Charts for the RESET pulse input timing. The A/D converter can operate at fC (Min) = 140 MSPS in this mode.
4-1415
HI3086
CLK
HI3086 CLK CLK A 6-BITS
CLKOUT DATA
RESETN
HI3086 CLK B 6-BITS
CLKOUT DATA
RESETN
FIGURE 8. WHEN THE RESET PULSE IS NOT USED
CLK RESET PULSE HI3086 CLK CLK A 6-BITS DATA CLKOUT
RESETN
HI3086 CLK RESET PULSE B 6-BITS
CLKOUT DATA
RESETN
FIGURE 9. WHEN THE RESET PULSE IS USED
Straight Mode (See Figures 22, 23, 24 and 25). Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. The A/D converter can operate at fC (Min) = 100 MSPS in this mode.
Digital Input Level and Supply Voltage Settings The logic input level for the HI3086 supports ECL, PECL and TTL levels. The power supplies (DVEE3 , DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level.
TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS DIGITAL INPUT LEVEL ECL PECL TTL
DVEE3 -5V 0V 0V
DGND3 0V +5V +5V
SUPPLY VOLTAGE 5V +5V +5V
APPLICATION CIRCUITS Figures 19, 22 Figures 20, 23 Figures 21, 24, 25
4-1416
HI3086 Timing Waveforms
N-1 VIN tDS t N N+1 N+2
N+3
CLK tPW1 tPW0 P1D0 TO D5 tDO2 N-2 2.0V 0.8V 2.0V 0.8V tDO1 t + 1ns 2.0V 0.8V tRS RESET PULSE tRH 2.0V 0.8V N
N+2
P2D0 TO D5 tDCLK
N-3
N-1
N+1
t
t
CLK OUT
FIGURE 10. DEMUX MODE TIMING CHART (SELECT = VCC)
N-1 VIN N+1 tDS N t CLK tPW1 tPW0 2.0V 0.8V 2.0V 0.8V
N+2 N+3
P1D0 TO D5
N-4
N-3
N-2
N-1
N
P2D0 TO D5
N-5
N-4
N-3
N-2
N-1
tD02 CLK OUT (CLK IS INVERTED AND OUTPUT) 2.0V 0.8V tDCLK
RESET PULSE
FIGURE 11. STRAIGHT MODE TIMING CHART (SELECT = GND)
4-1417
HI3086 Notes on Operation
* The HI3086 is a high-speed A/D conver ter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. * The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows: - The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. - To prevent interference between AGND and DGND and between AVCC and DVCC , make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVCC and DVCC lines at one point each via a ferrite-bead filter. Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. - Ground the power supply pins (AVCC , DVCC1 , DVCC2 , DVEE3) as close to each pin as possible with a 0.1F or larger ceramic chip capacitor. (Connect the AVCC pin to the AGND pattern and the DVCC1 , DVCC2 , DVEE3 pins to the DGND pattern.) - The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. * The analog input pin V IN has an input capacitance of approximately 7pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit; keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. * The V RT and V RB pins must have adequate bypass to protect them from high-frequency noise. Bypass them to AGND with approximately 1F tantal capacitor and, 0.1F chip capacitor as short as possible. * The offset for residual is generated each for the reference voltage pins VRT and VRB . When the offset voltage has no influence on the IC operation, the voltage should be applied to the VRT and VRB pins directly, keeping the VRBS pin open. When the reference voltage is to be supplied to these pins precisely, form the feedback loop circuit with VRT and VRB as a force pin and adjust the offset voltage to be 0V. See Figure 25 for details. * If the CLKN/E pin is not used, bypass this pin to DGND with an approximately 0.1F capacitor. At this time, approximately DGND3 -1.2V voltage is generated. However, this is not recommended for use as threshold voltage VBB as it is too weak. * When the digital input level is ECL or PECL level, ***/E pins should be used and ***/T pins left open. When the digital input level is TTL, ***/T pins should be used and ***/E pins left open.
Typical Performance Curves
70 CURRENT CONSUMPTION (mA) CURRENT CONSUMPTION (mA)
90
65
80
60
70
55
60 -1kHz 4 DEMUX MODE CL = 5pF 0 70 CONVERSION RATE (MSPS) 140 fIN = fCLK
50 -25 25 AMBIENT TEMPERATURE (oC) 75
50
FIGURE 12. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE CHARACTERISTICS
FIGURE 13. CURRENT CONSUMPTION vs CONVERSION RATE CHARACTERISTICS
4-1418
HI3086 Typical Performance Curves
VRT = 4V VRB = 2V 100 ANALOG INPUT CURRENT (A) REFERENCE CURRENT (mA)
(Continued)
11
10
9
50
8
7 0 2 3 ANALOG INPUT VOLTAGE (V) 4 -25 25 AMBIENT TEMPERATURE (oC) 75
FIGURE 14. ANALOG INPUT CURRENT vs ANALOG INPUT VOLTAGE CHARACTERISTICS
40 fC = 140 MSPS
FIGURE 15. REFERENCE CURRENT vs AMBIENT TEMPERATURE CHARACTERISTICS
10-6
fIN =
-1kHz 4 ERROR > 4 LSB
fCLK
10-7 35 ERROR (TPS) SNR (dB)
10-8
10-9
30 1 3 5 10 30 50 100
10-10 140 160 180 200
INPUT FREQUENCY (MHz)
CONVERSION RATE (MSPS)
FIGURE 16. SNR vs INPUT FREQUENCY RESPONSE
FIGURE 17. ERROR RATE vs CONVERSION RATE CHARACTERISTICS
MAXIMUM CONVERSION RATE (MSPS)
180
fIN =
-1kHZ 4 ERROR > 4 LSB ERROR RATE: 10-9 TPS
fCLK
170
160
150
140 -25 25 AMBIENT TEMPERATURE (oC) 75
FIGURE 18. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS
4-1419
HI3086 Application Circuits
6-BIT DIGITAL DATA ECL RESET PULSE +5V (D) DG DG 12 11 10 9 -5V (D) AG 2V AG +5V (A) 13 14 15 16 17 18 AG -5V (A) AG AG DG 4V 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ECL - CLK DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA LATCH 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG +5V (D) P2D0 TO P2D5 6-BIT DIGITAL DATA LATCH
6-BIT DIGITAL DATA
FIGURE 19. DEMUX ECL INPUT
6-BIT DIGITAL DATA PECL RESET PULSE +5V (D) DG DG P2D0 TO P2D5 6-BIT DIGITAL DATA LATCH
12 11 10 9 DG AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG +5V (D) 4V 19 20 21 22 23 24
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG +5V (D)
25 26 27 28 29 30 31 32 33 34 35 36 PECL - CLK DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA LATCH
6-BIT DIGITAL DATA
FIGURE 20. DEMUX PECL INPUT
4-1420
HI3086 Application Circuits
(Continued)
6-BIT DIGITAL DATA TTLL RESET PULSE +5V (D) DG DG P2D0 TO P2D5 6-BIT DIGITAL DATA LATCH
12 11 10 9 DG AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG +5V (D) 4V 19 20 21 22 23 24
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG +5V (D) DG +5V (D)
25 26 27 28 29 30 31 32 33 34 35 36 DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA LATCH
TTL - CLK
6-BIT DIGITAL DATA
FIGURE 21. DMUX TTL INPUT
+5V (D) DG
DG
12 11 10 9 -5V (D) AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG DG 4V 19 20 21 22 23 24
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG DG +5V (D) DG +5V (D)
25 26 27 28 29 30 31 32 33 34 35 36 ECL - CLK DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA LATCH
6-BIT DIGITAL DATA
ECL TTL
FIGURE 22. STRAIGHT ECL INPUT
4-1421
HI3086 Application Circuits
(Continued)
+5V (D) DG
DG
12 11 10 9 DG AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG +5V (D) 4V 19 20 21 22 23 24
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG DG +5V (D) DG +5V (D)
25 26 27 28 29 30 31 32 33 34 35 36 PECL - CLK DG +5V (D) DG P1D0 TO P1D5 6-BIT DIGITAL DATA LATCH
6-BIT DIGITAL DATA
PECL TTL
FIGURE 23. STRAIGHT PECL INPUT
+5V (D) DG
DG
12 11 10 9 DG AG 2V AG +5V (A) 13 14 15 16 17 18 AG +5V (A) AG AG +5V (D) 4V 19 20 21 22 23 24
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 +5V (D) DG DG +5V (D) DG +5V (D)
25 26 27 28 29 30 31 32 33 34 35 36 DG +5V (D) DG P1D0 TO P1D5 8-BIT DIGITAL DATA LATCH
TTL - CLK
6-BIT DIGITAL DATA
FIGURE 24. STRAIGHT TTL INPUT
4-1422
HI3086 Application Circuits
(Continued)
AG 1F 4V ANALOG INPUT AG AG 1F VRTS 10F +5V (A) AG AG
+ -
+SHORT
+ -
2V
VRBS SHORT
DG
24 DGND3
23 AGND
22 VRTS
21 VRT
20 AVCC
19 VIN
18 NC
17 AVCC
16 VRB
15 VRBS
14 AGND
13 DVEE3 RESETN/E 12 RESET/E 11 RESETN/T 10 DVCC2 DGND2 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 9 8 7 6 5 4 3 2 1 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 (LSB) (MSB) DGND2 48 DVCC2
25 26 TTL CLK 27 28 29 (LSB) P1D0 P1D1 P1D2 P1D3 P1D4 (MSB) P1D5 30 31 32 33 34 35 36
CLK/E CLKN/E CLK/T DVCC2 DGND2 P1D0 P1D1 P1D2 P1D3 P1D4 P1D5 CLKOUT DGND2 SELECT DGND1 DVCC2 DVCC1 INV
DGND1 46
37
38
39
40
41
42
43
44
45
47
10F
+
DG +5V (D)
SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION IS THE CHIP CAPACITOR OF 0.1F.
FIGURE 25. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED)
4-1423
CLKOUT
DVCC1
NC
NC
PS
HI3086
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
4-1424

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